Synchronous bus and Asynchronous bus

       Synchronous bus:

1. In synchronous bus, all devices derive timing information from a common

       clock signal.

1. Fig. 2 shows the timing diagram for synchronous input transfer.

Fig. 2

1. At time to, the processor places the device address on the address lines of system but and sets the control lines to perform the input operation, during time t1 – t1, address devices gets the address. At time t1, address devices place its data on the data bus, and at time t2, the processor reads the data lines and loads the data from data bus into its input buffer.

Asynchronous bus:

1. In this the common clock is eliminated and data transfer on the system bus is achieved by use of a hand shake between the processor and the device being addressed. Here the clock line is replaced by two control signals ready and accept.
2. Fig. 3 shows timing dig, for asynchronous input transfer.