SIM (set interrupt mask)

SIM set interrupt mask is used for interrupts handling in 8085: It implies that the instruction mask the interrupts. However the instruction must be executed in order to use the interrupts.It having the following functions:

1. To set the RST 7.5, 6.5 and 5.5 interrupts.
2. To Reset RST 7.5 Flip Flop.
3. To Implement series I/O transmit D7 bit  to transmit data.

DMA dada transfer:

 DMA dada  transfer:

1. For some  application, such  as  transferring  dada  bytes to  memory  form  magnetic  or optical  disk, however, the  dada  bytes  are coming  in from  the  disk  faster  then  they  can  be  read in  with  program  instruction. In a case like this we use a dedicated Hardware device called a direct memory access (DMA) controller to manage the data transfer.
2. The DMA controller temporarily borrows the address bus, data bus, and control bus from the microprocessor and transfer the data by directly from the disk controller to a series of memory location.
3. A DMA controller can also transfer data from memory to a port.

Instruction queue in 8086 microprocessor.

Function of instruction queue in 8086 microprocessor.
Ans.:      
  The EU is decoding or  executing  an instruction  which does not require  use  of the buses,  the BUI fetches up to six instruction bytes  for  the  following  instructions . the BUI stores  these  prefetched  bytes  in a first –in -irst –out  register  set  called a queue

When  the  EU is ready  for  it’s next  instruction , it  simply  reads  the  instruction   bytes  for  the  instruction  from  the  queue  in the  BUI     

This  is much  faster  than  sending  out  an  address to the system  memory  and  waiting  out  memory  to  send  back  the next  instruction  byte  or  bytes

8251 programmable communication interface chip

Applications of 8251 programmable communication interface chip.
Ans.:
8251 is programmable communication interface. Which is used as Universal Asynchronous Receiver Transmitter. (UART 8251), which is modeled on the peripheral interface device adapter.
     It consists:

1. a serial transmit block.
2. a serial receive block.
3. a CPU interface (I/f) block
4. 8251 is used as program control device.

Program Counter in 8085 microprocessor

 Requirement of a program counter in 8085 microprocessor.

Program counter hold the address of either the first byte of the next instruction to be fetched for execution or the address of the next by byte of instruction. Which has been completely fetched. In both the cases it gets incremented automatically one by one as the instruction byte get fetched. Also program register keeps the address of next instruction.

Synchronous bus and Asynchronous bus

       Synchronous bus:

1. In synchronous bus, all devices derive timing information from a common

       clock signal.

1. Fig. 2 shows the timing diagram for synchronous input transfer.

Fig. 2

1. At time to, the processor places the device address on the address lines of system but and sets the control lines to perform the input operation, during time t1 – t1, address devices gets the address. At time t1, address devices place its data on the data bus, and at time t2, the processor reads the data lines and loads the data from data bus into its input buffer.

Asynchronous bus:

1. In this the common clock is eliminated and data transfer on the system bus is achieved by use of a hand shake between the processor and the device being addressed. Here the clock line is replaced by two control signals ready and accept.
2. Fig. 3 shows timing dig, for asynchronous input transfer.

PSW : PROGRAM STATUS WORD

PSW (program status word) : Program status word refers to the accumulator and flag register, this PSW will store the current data or the content of the accumulator and flag register while execution of program.
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